CB664 i2c clock distribution buffer for three banks of mobile sdram approved product cypress semiconductor corporation 525 los coches st. document#: 38-07024 rev. ** 5/6/99 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 1 of 8 http://www.cypress.com product features ? 7 output buffer for high clock fanout applications. ? output may be individually disabled with i 2 c ? vdd = 3.3 volts ? output frequency range 10 mhz to 100 mhz ? <250ps skew between output clocks. ? 16-pin ssop and tssop package. block diagram 1 2 2 2 vdd sdr(0:1) sdr2 sdr(3:4) sdr(5:6) i 2 c control sdata sclk refin product description the device is a high fanout system clock buffer. its primary application is to distribute clocks needed to support a wide range of applications such as sdram clocks. this device provides low skew distribution clock heavily loaded. one important application of this component is where long traces are used to transport clocks from their generating devices to their loads. the creation of emi and the degradation of waveform rise and fall times is greatly reduces by running a single reference clock trace to this device and then using it to these devices emi is therefore minimized and board real estate is saved. pin configuration vdd s dr 0 sdr1 vss c lkin s dr2 vdd s dr 6 sdr5 vdd v ss s dr4 s dr 3 vss s dat a sc lk 1 2 3 4 5 6 8 7 1 6 1 5 14 1 3 12 11 9 1 0
CB664 i2c clock distribution buffer for three banks of mobile sdram approved product cypress semiconductor corporation 525 los coches st. document#: 38-07024 rev. ** 5/6/99 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 2 of 8 http://www.cypress.com pin description pin no. pin name pwr i/o type description 5 clkin vdd i pad this pin is connected to the input reference clock. this clock be in the range of 10.0 to 100.0 mhz 2,3,6,11,12,15,16 sdr(0:6) vdd o buf1 low skew output clock. 8 sdata - i/o pad serial data of i 2 c-wire control interface. has internal pull-up resistor. 9 sclk - i pad serial data of i 2 c-wire control interface. has internal pull-up resistor 4,10,14 vss - - - common ground 1,7,13 vdd - - - power for output clock buffers and core logic maximum ratings maximum input voltage relative to vss: vss ? 0.3v maximum input voltage relative to vdd: vdd + 0.3v storage temperature: 0 o to +125 o c operating temperature: 0 o to +70 o c maximum power supply: 7v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, vin and vout should be constrained to the range: vss<(vin or vout) CB664 i2c clock distribution buffer for three banks of mobile sdram approved product cypress semiconductor corporation 525 los coches st. document#: 38-07024 rev. ** 5/6/99 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 3 of 8 http://www.cypress.com 2-wire i 2 c control interface the 2-wire control interface implements a write only slave interface. the device control be read back. sub- addressing is not supported, thus, all preceding bytes must be sent in order to change one of the control bytes. the 2-wire control interface allows each clock output to be individually enabled or disabled. during normal data transfer, the sdata signal only changes when the sdclk signal is low, and is stable when sdclk is high. there are two exceptions to this. a high to low transition on sdata while sdclk is high is used to indicate the start of a data transfer cycle. a low to high transition on sdata while sdclk is high indicates the end of data transfer cycle. data is always sent as complete 8-bit bytes, after which an acknowledge is generated. the first byte of a transfer cycle is a 7-bit address with a read /write bit as the lsb. data is being transferred msb first. the device respond to writes to 10 bytes (max) of data to address d2 by generating the acknowledge (low) signal on the sdata wire following reception of each byte. the device will not respond to any other control interface conditions. control signal registers note : the pin# column lists the affected pin number where applicable. the @pup column gives the state at true power up. bytes are set to the values shown only on true power up, and not when the pwr_dwn# pin is activated. following the acknowledge of the address byte ( d2) two additional bytes must be sent: 1. ? command code? byte and 2. ?byte count? byte although the data (bits) in these two bytes are considered ? don?t care?, they must be sent and will be acknowledge. after the command code and the count bytes have been acknowledge, the below described sequence (byte0, byte1, byte2?) will be valid and acknowledged. byte 0 : (1= enable, 0= stopped) byte 1: (1= enable, 0= stopped) bit @pup pin # description 7 1 6 sdr2(enable =1,stopped=0) 6 1 - reserved 5 1 - reserved 4 1 - reserved 3 1 3 sdr1(enable =1,stopped=0) 2 1 2 sdr0(enable =1,stopped=0) 1 1 - reserved 0 1 - reserved see application note an664-01 for further reducing power consumption with i 2 c bit @pup pin # description 7 1 16 sdr6 (enable=1,s topped=0) 6 1 15 sdr5 (enable=1, stopped=0 ) 51 -reserved 41 -reserved 3 1 12 sdr4 (enable=1, stopped=0) 2 1 11 sdr3 (enable=1, stopped=0) 11 -reserved 01 -reserved
CB664 i2c clock distribution buffer for three banks of mobile sdram approved product cypress semiconductor corporation 525 los coches st. document#: 38-07024 rev. ** 5/6/99 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 4 of 8 http://www.cypress.com electrical characteristics characteristics symbol min typ max units conditions input low voltage vil - - 0.8 vdc - input high voltage vih 2.0 - - vdc - input low current iil -66 a input high current iih 66 a tri-state leakage current ioz - - 10 a idd 66 9 100 ma input frequency = 66 mhz dynamic supply current (all outputs loaded with 30 pf) idd 100 12 - 140 ma input frequency =100 mhz static supply current isdd - - 1 ma all outputs disabled no input clock short circuit current isc 25 - - ma 1 input at a time ? 30 seconds input rise time vir 2.4 - - ns 0.8 to 2.4 volts vdd =vdd1 thru vdd6 = 3.3v 5%, ta = 0 c to 70 c switching characteristics characteristics symbol min typ max units conditions output duty cycle - 45 50 55 % measured at 1.5v (50/50 in) buffer out/out skew all buffer outputs tskew - - 250 ps 35 pf load measured at 1.5v buffer input to output skew tskew 2.0 0 5.0 ns jitter cycle to cycle* tjcc 50 ps @35 pf loading jitter absolute (peak to peak)* tjabs 150 ps @35 pf loading vdd =vdd1 thru vdd6 = 3.3v 5%, ta = 0 c to 70 c * this jitter is additive to the input clock?s jitter buffer characteristics ( all clock outputs) characteristics symbol min typ max units conditions pull-up current min ioh min - - -54 ma vout = 1.0 v ull-up current max ioh max - - 30 ma vout = 2.6 v pull-down current min iol min - - 54 ma vout = 1.2 v pull-down current max iol max - - 23 ma vout = 0.4 v rise/fall time min between 0.4v and 2.4v trf min - - 1.33 ns 30 pf load rise/fall time max between 0.4v and 2.4v trf max - - 1.33 ns 30 pf load vdd = vddi thru vdd6 = 3.3v 5%, ta = 0 c to +70 c
CB664 i2c clock distribution buffer for three banks of mobile sdram approved product cypress semiconductor corporation 525 los coches st. document#: 38-07024 rev. ** 5/6/99 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 5 of 8 http://www.cypress.com pcb layout suggestion this is only a layout recommendation for best performance and lower emi. the designer may choose a different approach but c1, c2, c3 (all are o.1 f) should always be used and placed as close to their vdd pins as is physically possible . fb1 or r1 is a ferrite bead or resistor as needed to reduce conducted emi from the device into the systems power circuitry. void (cut) in power plane 1 2 3 4 5 6 7 8 c1 c2 16 15 14 13 12 11 10 9 c3 fbi or r1 vcc c7 6.8 to 22
CB664 i2c clock distribution buffer for three banks of mobile sdram approved product cypress semiconductor corporation 525 los coches st. document#: 38-07024 rev. ** 5/6/99 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 6 of 8 http://www.cypress.com package drawing and dimensions 16 pin tssop outline dimensions inches millimeters symbol min nom max min nom max a - - 0.047 - - 1.20 a 1 0.002 - 0.006 0.05 - 0.15 a2 0.031 0.039 0.041 0.80 1.00 1.05 b 0.007 - 0.012 0.19 - 0.30 c 0.004 - 0.008 0.09 - 0.20 d 0.193 0.197 0.201 4.90 5.00 5.10 e 0.169 0.173 0.177 4.30 4.40 4.50 e 0.026 bsc 0.65 bsc h 0.244 0.252 0.260 6.20 6.40 6.60 l 0.018 0.024 0.030 0.45 0.60 0.75 a 0o - 8o 0o - 8o 16 pin ssop outline dimensions inches millimeters symbol min nom max min nom max a 0.068 0.073 0.078 1.73 1.86 1.99 a 1 0.002 0.005 0.008 0.05 0.13 0.21 a2 0.066 0.068 0.070 1.68 1.73 1.78 b 0.010 0.012 0.015 0.25 0.30 0.38 c 0.005 0.006 0.009 0.13 0.15 0.22 d 0.239 0.244 0.249 6.07 6.20 6.33 e 0.205 0.209 0.212 5.20 5.30 5.38 e 0.0256bsc 0.65 bsc h 0.301 0.307 0.311 7.65 7.80 7.90 l 0.022 0.030 0.037 0.55 0.75 0.95 a 0 4 8 0 4 8 a b e a a 1 a 2 d e h l c
CB664 i2c clock distribution buffer for three banks of mobile sdram approved product cypress semiconductor corporation 525 los coches st. document#: 38-07024 rev. ** 5/6/99 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 7 of 8 http://www.cypress.com ordering information part number package type production flow CB664et 16 pin tssop commercial, 0oc to +70oc CB664ey 16 pin ssop commercial, 0oc to +70oc note: the ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. marking: example: imi, yywww CB664et lot # CB664et package t = tssop revision device number disclaimer cypress semiconductor corporation reserves the right to change or modify the information contained in this datasheet and the products described therein, without prior notice. cypress semiconductor corporation does not convey any license under its patent rights nor the rights of others. charts, drawings and schedules contained in this datasheet are provided for illustration purposes only and they vary depending upon specific applications. cypress semiconductor corporation makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does cypress semiconductor corporation assume any liability arising out of the application or use of any product or circuit described herein. cypress semiconductor corporation does not authorize use of its products as critical components in any application in which the failure of the cypress semiconductor corporation product may be expected to result in significant injury or death, including life support systems and critical medical instruments.
CB664 i2c clock distribution buffer for three banks of mobile sdram approved product cypress semiconductor corporation 525 los coches st. document#: 38-07024 rev. ** 5/6/99 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 8 of 8 http://www.cypress.com document title: CB664 i2c clock distribution buffer for three banks of mobile sdram document number: 38-07024 rev. ecn no. issue date orig. of change description of change ** 109163 08/29/01 ndp convert from imi to cypress
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